Main

Other useful info





Last modified 2007-05-02

PLL0305A

Serial input PLL frequency synthesizer


Overview

PLL0305A is a PLL syntheseizer where input frequency divider ratio can be set by external serial data.
The reference frequency divider ratio can be selected from 8 choices stored in a built-in ROM.


Features

  • 30 MHz Fin
  • 15 MHz Fosc
  • Reference frequency divider ratios from 16 to 8192
  • Input frequency divider ratios from 5 to 16383
  • Lock detector pin
  • Can be used with active or passive filters

PinNameDescription
1RA 1
2RA 2
3ÝVOutput for differential LowPassFilter
4ÝROutput for differential LowPassFilter
5Vcc4,5Volt to 5,5Volt
6PDPPassive filter
7GND
8LDLoop Detect - Unlocked = Low and Locked = High
9F inFrequency input
10CLOCK
11DATASerial data input
12ENABLE
13PDAActive filter
14TESTFactory test
15REF outReference frequency out
16X outXTAL output
17X inXTAL input
18RA 0


RA2RA1RA0Divider ratio
00016
001512
0101024
0112048
1003668
1014096
1106144
1118192

Timing Diagram
WINTransceiver tsu1 = 300 nS
WINTransceiver tsu2 = 300 nS
WINTransceiver tH = 300 nS


Input frequency divider data setting

Input data MSB first.
Data is input on the rising edge of CLOCK.
While the ENABLE signal is "H", data is transferred from shift register to input frequency divider.
Data setting