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Last modified 2007-05-02

PLL03A and PLL08A

PLL frequency synthesizer

Overview

This 27 MHz band, PLL frequency synthesizer LSI chip is designed specifically for CB transceivers.
It incorporates PLL circuitry and a controller for CB applications on a single CMOS chip.
The PLL-circuit use a 7 bit ROM programmable divide-by-N counter. The ROM-table is programmed from factory to 40 channels.

PinNameDescription
1VccPositive supply voltage
2RIReferency oscillator input
3LD1Loop detected 1
4LD2Loop detected 2
5LD3Loop detected 3
6PDPhase detector output
7T/RTransmit=High Receive=Low
8F inVCO frequency input
9P6Programmable input 6
10P5Programmable input 5
11P4Programmable input 4
12P3Programmable input 3
13P2Programmable input 2
14P1Programmable input 1
15P0Programmable input 0
16GNDGround

Programming Chart for
PLL03A (U.S. - AM)
PLL08A (EEC - FM)

ChannelRX
Divided by
TX
Divided by
112061297
212081299
..........
2212581349
..........
4012941385

NOTES:
  1. Special divided-by-2 circuit in TX mode change referency divider output to 2.5kHz steps.
  2. 91-count upshifts on TX provides 455kHz offset for receiver IF mixing when VCO frequency is doubled.
  3. Since chip cannot divide VCO directly, it is down-mixed with the 10.240 MHz referency oscillator signal, producing
    6 MHz outputs (RX Mode) and 3 MHz outputs (TX Mode) into dividers. Standard 16 MHz VCO is used.
  4. PLL08A contains only the first 22 FCC channels for EEC use, otherwise both chips are identical.
Example of VCO determination, channel 1:
1206 x 5 kHz + 10.240 MHz = 16.270 MHz (RX-Mode)
1297 x 2.5 kHz + 10.240 MHz = 13.4825 MHz (TX-Mode)
(13.4825 MHz x 2 = 26.965 MHz)