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Last modified 2007-05-02

MC145106, MM55106, MM55116 and MM55126

PLL frequency synthesizer


The MC145106 is a phase–locked loop (PLL) frequency synthesizer constructed in CMOS on a single monolithic structure. This synthesizer finds applications in such areas as CB and FM transceivers. The device contains an oscillator/amplifier, a 1024 or 2048 divider chain for the oscillator signal, a programmable divider chain for the input signal, and a phase detector.

The MC145106 has circuitry for a 10.24 MHz oscillator or may operate with an external signal. The circuit provides a 5.12 MHz output signal, which can be used for frequency tripling. A 512 programmable divider divides the input signal frequency for channel selection. The inputs to the programmable divider are standard ground–to–supply binary signals. Pull-down resistors normally set these programmable inputs to ground, enabling them to be controlled from a mechanical switch or electronic circuitry.

The phase detector may control a VCO and yields a high level signal when input frequency is low, and a low level signal when input frequency is high. An out-of-lock signal is provided from the on-chip lock detector with a "0" level for the out-of-lock condition.
  • Single power supply
  • Wide supply range: 4.5 to 12 V
  • Provision for 10.24 MHz XTAL oscillator
  • 5.12 MHz output
  • Programmable division binary input selects up to N=512
  • On-chip pull-down resistors on programmable divider inputs
  • Selectable reference divider, 1024 or 2048 (including 2)
  • Tri-state phase detector

Down-converting of the frequency to the divider

This PLL circuit use a mixer and a XTAL oscillator to convert the output frequency f OUT to the f IN to the PLL Circuit.
The XTAL frequency is f XTAL = f OUT - f IN
The output frequency can be changed by changing the mixing-XTAL or add a new mixing-XTAL to the oscillator.

1VDDPositive power supply
2F inFrequency input to programmable divider - Max 3 MHz
3OSC inOscillator input
4OSC outOscillator output
5F outReference OSC frequency divide by 2 output
6FSReference oscillator frequency division select. 1=10 kHz, 0=5 kHz
7D outDetector output (for control of external VCO)
8LDLock detector
9P8Programmable inputs (Binary)
10P7Programmable inputs (Binary)
11P6Programmable inputs (Binary)
12P5Programmable inputs (Binary)
13P4Programmable inputs (Binary)
14P3Programmable inputs (Binary)
15P2Programmable inputs (Binary)
16P1Programmable inputs (Binary)
17P0Programmable inputs (Binary)

See also the explanation of PLL pin functions